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VNQ830P-E
QUAD CHANNEL HIGH SIDE DRIVER
TARGET SPECIFICATION
Table 1. General Features
TYPE VNQ830P-E
(*) Per each channel
Figure 1. Package
IOUT 6 A (*) VCC 36 V
RDS(on) 65 m (*)
CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s PROTECTION AGAINST LOSS OF GROUND s VERY LOW STAND-BY CURRENT s REVERSE BATTERY PROTECTION (**) s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE
s s
SO-28 (DOUBLE ISLAND)
DESCRIPTION The VNQ830P-E is a quad HSD formed by assembling two VND830-E chips in the same SO28 package. The VND830-E is a monolithic device made by using| STMicroelectronics VIPower M0-3 Technology. The VNQ830P-E is intended for driving any type of multiple loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes
Package SO-28
Note: (**) See application schematic at page 11.
Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.
Tube VNQ830P-E
Tape and Reel VNQ830PTR-E
Rev. 1 October 2004 1/21 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
VNQ830P-E
Figure 2. Block Diagram
VCC1,2
Vcc CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND1,2
CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2
INPUT1
STATUS1 CURRENT LIMITER 1 LOGIC OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD ON 2 DRIVER 2 OUTPUT2
OPENLOAD OFF 2 OVERTEMP. 2 VCC3,4 Vcc CLAMP
OVERVOLTAGE UNDERVOLTAGE
GND3,4 INPUT3
CLAMP 3 OUTPUT3 DRIVER 3 CLAMP 4
STATUS3 CURRENT LIMITER 3 LOGIC OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 OPENLOAD ON 4 DRIVER 4 OUTPUT4
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VNQ830P-E
Table 3. Absolute Maximum Ratings
Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge R=1.5K; C=100pF) VESD - INPUT - STATUS - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tstg (L=1.5mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=9A) Power dissipation (per island) at Tlead=25C Junction Operating Temperature Storage Temperature 85 6.25 Internally Limited - 55 to 150 mJ W C C (Human Body Model: 4000 4000 5000 5000 V V V V Parameter Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
VCC1,2 GND 1,2 INPUT1 STATUS1 STATUS2 INPUT2 VCC1,2 VCC3,4 GND 3,4 INPUT3 STATUS3 STATUS4 INPUT4 VCC3,4 14 15 1 28 VCC1,2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4 VCC3,4
Connection / Pin Floating To Ground
Status X
N.C. X X
Output X
Input X Through 10K resistor
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Figure 4. Current and Voltage Conventions
IS3,4 VCC3,4 IIN1 VIN1 VSTAT1 VIN2 VSTAT2 VIN3 VSTAT3 ISTAT1 IIN2 ISTAT2 IIN3 ISTAT3 IIN4 INPUT1 STATUS1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 GND3,4 IGND3,4 OUTPUT3 IOUT4 OUTPUT4 GND1,2 IGND1,2 VOUT4 VOUT3 OUTPUT2 IOUT3 VOUT2 OUTPUT1 IOUT2 IOUT1 VOUT1 VCC3,4 VCC1,2 IS1,2 VF1 (*) VCC1,2
VIN4 ISTAT4 VSTAT4
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data (Per island)
Symbol Rthj-case Rthj-amb Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient (one chip ON) Thermal resistance junction-ambient (two chips ON) (MAX) (MAX) (MAX) Value 15 60 (1) 46 (1) 44 (2) 31 (2) Unit C/W C/W C/W
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. Note: 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
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VNQ830P-E
ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) VUSD (**) VOV (**) Ron Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance IOUT=2A; Tj=25C IOUT=2A; VCC>8V Off State; VCC=13V; VIN=VOUT=0V IS (**) Supply Current Off State; VCC=13V; VIN=VOUT=0V; Tj =25C On State; VCC=13V; VIN=5V; IOUT=0A IL(off1) IL(off2) IL(off3) IL(off4) Off State Output Current Off State Output Current Off State Output Current Off State Output Current VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C 0 -75 12 12 5 Test Conditions Min. 5.5 3 36 65 130 40 25 7 50 0 5 3 Typ. 13 4 Max. 36 5.5 Unit V V V m m A A mA A A A A
Note: (**) Per island.
Table 6. Switching (Per each channel) (V CC =13V)
Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Test Conditions RL=6.5 from VIN rising edge to VOUT=1.3V RL=6.5 from VIN falling edge to VOUT=11.7V RL=6.5 from VOUT=1.3V to VOUT=10.4V RL=6.5 from VOUT=11.7V to VOUT=1.3V Min. Typ. 30 30 See relative diagram See relative diagram V/s Max. Unit s s
Turn-on Voltage Slope
V/s
Turn-off Voltage Slope
Table 7. VCC - Output Diode
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=1.2A; Tj=150C Min Typ Max 0.6 Unit V
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VNQ830P-E
ELECTRICAL CHARACTERISTICS (continued) Table 8. Logic Input (Per each channel)
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage IIN=1mA IIN=-1mA VIN=3.25V 0.5 6 6.8 -0.7 8 VIN=1.25V 1 3.25 10 Test Conditions Min. Typ. Max. 1.25 Unit V A V A V V V
Table 9. Status Pin (Per each channel)
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status Low Output Voltage Status Leakage Current Status Pin Input Capacitance Status Clamp Voltage Test Conditions ISTAT=1.6mA Normal Operation; VSTAT=5V Normal Operation; VSTAT=5V ISTAT=1mA ISTAT=-1mA 6 6.8 -0.7 Min Typ Max 0.5 10 100 8 Unit V A pF V V
Table 10. Protections (Per each channel) (See note 3)
Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage Tj>TTSD 6 5.5VNote: 3. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
Table 11. Openload Detection (Per each channel)
Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 50 Typ 100 Max 200 200 Unit mA s V s
3.5 1000
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VNQ830P-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL VINn VINn
OVER TEMP STATUS TIMING Tj > TTSD
VSTATn VSTATn tSDL tDOL(off) tDOL(on) tSDL
Figure 6. Switching time Waveforms
VOUTn 90% 80%
dVOUT/dt(on)
dVOUT/dt(off)
10% t VINn
td(on)
td(off)
t
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Table 12. Truth Table
CONDITIONS Normal Operation INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
Current Limitation
Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL
Table 13. Electrical Transient Requirements on VCC Pin
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
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Figure 7. Waveforms
NORMAL OPERATION INPUTn LOAD VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VUSD INPUTn LOAD VOLTAGEn STATUS undefined
VCC
OVERVOLTAGE VCCVOL VOL VCC>VOV
OPEN LOAD without external pull-up INPUTn LOAD VOLTAGEn STATUSn OVERTEMPERATURE
Tj INPUTn LOAD CURRENTn STATUSn
TTSD TR
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Figure 8. Application Schematic
+5V +5V +5V VCC1,2 Rprot STATUS1 VCC3,4
Rprot
INPUT1 Dld
Rprot
STATUS2
OUTPUT1
Rprot
C
INPUT2
Rprot
STATUS3
OUTPUT2
Rprot
OUTPUT3 INPUT3
Rprot
STATUS4 OUTPUT4 INPUT4 GND1,2 GND3,4
Rprot
RGND +5V +5V VGND DGND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / 2(IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND 10/21
This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2.
VNQ830P-E
Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RLLOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax
Figure 9. Open Load detection in off state
V batt. VPU
VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2)
GROUND
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VNQ830P-E
Figure 10. Off State Output Current
IL(off1) (uA)
2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 175
Figure 11. High Level Input Current
Iih (uA)
5 4.5
Off state Vcc=36V Vin=Vout=0V
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 12. Input Clamp Voltage
Vicl (V)
8 7.8
Figure 14. Status Level Voltage
Ilstat (uA)
0.05
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175
0.04
Vstat=5V
0.03
0.02
0.01
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 13. Status Low Output Voltage
Vstat (V)
0.8 0.7
Figure 15. Status Clamp Voltage
Vscl (V)
8 7.8
Istat=1.6mA
0.6
Istat=1mA
7.6 7.4
0.5 0.4 0.3 0.2
7.2 7 6.8 6.6 6.4
0.1 0 -50 -25 0 25 50 75 100 125 150 175
6.2 6 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNQ830P-E
Figure 16. On State Resistance Vs Tcase
Ron (mOhm)
160 140 120 100 70 80 60 40 20 0 -50 -25 0 25 50 75 100 125 150 175 60 50 40 30 20 10 0 5 10 15 20 25 30 35 40
Figure 17. On State Resistance Vs VCC
Ron (mOhm)
120 110
Tc=150C
Iout=2A Vcc=8V; 13V & 36V
100 90 80
Tc=25C
Tc= - 40C
Iout=5A
Tc (C)
Vcc (V)
Figure 18. Openload On State Detection Threshold
Iol (mA)
150 140 130 120 110 100 90 80 70 60 50 -50 -25 0 25 50 75 100 125 150 175
Figure 20. Openload Off State Voltage Detection Threshold
Vol (V)
5 4.5
Vcc=13V Vin=5V
Vin=0V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 19. Input High Level
Vih (V)
3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Figure 21. Input Low Level
Vil (V)
2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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Figure 22. Turn-on Voltage Slope
dVout/dt(on) (V/ms)
800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 25. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
600 550
Vcc=13V Rl=6.5Ohm
Ri=6.5Ohm
500 450 400 350 300 250 200 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 23. Overvoltage Shutdown
Vov (V)
50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175
Figure 26. ILIM Vs Tcase
Ilim (A)
20 18
Vcc=13V
16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 24. Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
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VNQ830P-E
Figure 27. Maximum turn off current versus load inductance
ILMAX (A) 100
10
A B C
1 0.1 1 L(mH) 10 100
A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V VIN, IL Demagnetization
Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
Demagnetization
Demagnetization
t
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VNQ830P-E
SO-28 Thermal Data Figure 28. SO-28 DOUBLE ISLAND PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 3cm2, 6cm2).
Table 14. Thermal calculation according to the PCB heatsink area
Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1Pdchip2
Note:RthA = Thermal resistance Junction to Ambient with one chip ON Note:RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 Note:RthC = Mutual thermal resistance
Figure 29. Rthj-amb Vs PCB copper area in open box free air condition
RTHj_am b (C/W) 70 60 50
RthA
40 30 20 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7
RthB
RthC
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VNQ830P-E
Figure 30. SO-28 Thermal Impedance Junction Ambient Single Pulse
ZT H (C/W) 1000
One channel ON Two channels ON on same chip
100
0.5 cm2 6 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000
Figure 31. Thermal fitting model of a quad channels HSD in SO-28
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
Tj_1
= tp T
C1
C2
C3
C4
C5
C6
R1 Pd1
R2
R3
R4
R5
R6
Table 15. Thermal Parameter
Area/island (cm2) R1=R7=R13=R15 (C/W) R2=R8=R14=R16 (C/W) R3=R9 (C/W) R4=R10 (C/W) R5=R11 (C/W) R6=R12 (C/W) C1=C7=C13=C15 (W.s/C) C2=C8=C14=C16 (W.s/C) C3=C9 (W.s/C) C4=C10 (W.s/C) C5=C11 (W.s/C) C6=C12 (W.s/C) R17=R18 (C/W) 0.5 0.15 0.8 4.5 11 15 5 0.0006 2.10E-03 6.00E-03 0.2 1.5 5 150 6
Tj_2
C13
C14
R13 Pd2
R14
R17
R18
Tj_3
Pd3
C7
C8
C9
C10
C11
C12
R7
R8
R9
R10
R11
R12
13
Tj_4
C15
C16
R15 Pd4
R16
T_amb
8
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VNQ830P-E
PACKAGE MECHANICAL Table 16. SO-28 Mechanical Data
Symbol A a1 b b1 C c1 D E e e3 F L S 7.40 0.40 8 (max.) 17.7 10.00 1.27 16.51 7.60 1.27 0.10 0.35 0.23 0.50 45 (typ.) 18.1 10.65 millimeters Min Typ Max 2.65 0.30 0.49 0.32
Figure 32. SO-28 Package Dimensions
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VNQ830P-E
Figure 33. SO-28 TUBE SHIPMENT (no suffix)
C B
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
All dimensions are in mm.
28 700 532 3.5 13.8 0.6
A
Figure 34. TAPE AND REEL SHIPMENT (suffix "TR") REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 12 1.5 1.5 7.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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REVISION HISTORY Table 17. Revision History
Date Oct. 2004 Revision 1 First issue. Description of Changes
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VNQ830P-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved
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